|Hierarchical Design||Hardware Constraints||EE348/CS338|
Xilinx Foundation Tutorial
This is a brief tutorial for the Xilinx
Foundation Software. It targets first-time users who want to get
started with the Foundation Software to synthesize a digital
design. During the course of the tutorial, all steps of the
synthesis process are covered using a half-adder as running
example. We start with the input of the circuit in the schematic
editor, simulate the timing behavior of the circuit, compile it for an
XC4010XL FPGA, and test the design on an XS40/XStend prototyping
This tutorial is for the Foundation Series
Software, Version 1.4, running on the lab machines. In
particular, screen dumps have been generated from that version.
Several details in the Xilinx Student Edition deviate slightly from
this description. I explain the differences in the text.
The tutorial contains the following steps:
The following sections provide additional information:
In the Name
field of the New Project window type ``adder'' and click OK.
Now, a new project hierarchy is generated and is displayed in the left portion of
the Project Manager window in Figure 2. It contains
the file ``ADDER.UCF'', and directories ``ADDER'', ``SIMPRIMS'' and ``XC4000E''.
Note that a project is no more than a collection of files in a directory hierarchy. You
can figure out where your files are located, and browse through that hierarchy by
selecting the Open Project
item in the File menu of the
Note that the action of having generated a new project is logged in
the bottom part of the Project Manager window. We are now ready to create
a schematic for our half-adder.
A schematic is generated by inserting gates and input/output
pads. The inputs and outputs of the gates and pads are connected by means
of wires. Standard symbols such as the inverter ``INV'', the AND-gate
``AND2'', and the OR-gate ``OR2'' can be found in the ``Symbol Toolbox''.
The Symbol Toolbox is opened by a click on the button with the gate symbol
in the vertical toolbar on the left border of the Schematic Editor (buttom
eight from the bottom), or by pulling down the Mode
menu and selecting Symbols.
A screen dump of the Symbol Toolbox is shown in Figure
According to the naming convention in the symbol toolbox, gates are
listed by a (sort of) descriptive name, such as ``AND'' or ``OR''.
Most names end with a number, often describing the number of inputs into
the gate. For example, an AND-gate with two inputs and one output
is named ``AND2''. Analogously, the name for an OR-gate with two
inputs and one output is ``OR2''. Gates with a single input don't have
the number of inputs appended to the name, as for example for the inverter,
which is simply named ``INV''. You may insert a gate in the drawing
area of the Schematic Editor by left-clicking on the name in the Symbol Toolbox,
and by moving the cursor into the drawing area. The symbol for the gate appears
attached to the cursor. Moving the mouse drags the gate across the
drawing area. Left-clicking the mouse again in the drawing area causes
the gate symbol to be inserted at the current mouse position. This
process can be repeated until all gates are positioned approximately where
they are intended to end up. Figure 5 shows
the gates dropped for the half-adder.
Close the Symbol Toolbox by left-clicking on the Symbol
Toolbox bottom in the vertical toolbar or by double-clicking on the
top-left corner of the Symbol Toolbox window. We are now back in
editing (select and drag) mode, and can move the gates around by selecting
them with a left-click and dragging them across the drawing area.
Releasing the left mouse button drops the gate in the current position.
It is often convenient to use a grid for orientation. If not enabled in
your editor, pull down the View
menu and click on Grid.
Snapping all movements to the grid simplifies aligning the symbols even further.
A Snap to Grid
option can be found in the View
menu of the Schematic Editor as well.
The next step is to add input/output pads to our
collection of gates. Click on the terminal button (third from bottom of
the vertical button bar in the Schematic Capture window). A dialog
window entitled ``I/O Terminal'' appears. This situation is shown in Figure
6. In the Name
field type the terminal name ``A'', select Terminal
Type ``INPUT'', and click OK.
An input pad is now attached to the cursor. As with gates, drag the
terminal to its intended position in the drawing area and drop it with
a single left-click. Add another input pad named B, and two output
pads named SUM and CARRY to the schematic.
Three steps are required to produce a functional simulation of our half-adder circuit:
Click on signal ``A'' in the Signals Selection portion
of the window to select signal A, and add it to the waveform viewer by
the Add button in the lower left corner of the Component Selection window. Repeat the signal selection for signals ``B'', ``CARRY'', and ``SUM''. Finally, return to the waveform viewer by clicking button Close. The inputs and outputs are now displayed in the waveform viewer, cf. Figure 10.
The simplest way of adding a set of signals that
generates all possible combinations of truth values is the 16-bit binary
counter labeled Bc, which is represented by the row of 16 yellow LEDs in
the Stimulator Selection window. We can apply the sequence of truth
values 00, 01, 10, and 11 to the inputs A and B of the half-adder circuit
by assigning a Bc counter signal to the circuit inputs. Click on
signale name A
of input A in the Waveform Viewer window, and subsequently click on the
rightmost yellow LED of the Bc counter. As a result, the LSB of the
counter denoted B0 is assigned to input A. Assign counter signal
B1 to input B, and click on Close
to leave the Simulator Selection window.
Firstly, choose the clock period of the binary counter. Select the Preferences item in the Options pull-down menu of the Waveform Viewer window, cf. Figure 8. The Preferences window, shown in Figure 11, appears. In the Clocks section, select 100ns for the B0 period. Click the OK button to leave the Preferences window.
Secondly, choose the step sizes for the simulation.
There are two different step sizes to proceed with the simulation. Select
the Simulation Step
item in the Options
pull-down menu of the Waveform Viewer. The Step window, shown
in Figure 12, appears. Select ``100ns'' for
the Short Step
and ``500ns'' for the Long Step.
Click on the Set Step
button to save the selection, and on Close
to leave the Step window.
Thirdly, select the timing resolution of the Waveform
Viewer by clicking on the zoom buttons right above the list of signals
in the Waveform Viewer window until ``10ns/div'' appears.
Finally, the timing simulation can be performed by clicking one of the buttons ``short step'' (button with short foot step symbol to the right of the ON button) or ``long step'' (button with long foot step symbol to the left of the STOP button) repeatedly. Figure 13 shows the waveforms after executing one short step and two long steps.
An input buffer can be added by loading the Symbol Toolbox, and dragging an IBUF symbol next to the wire where it shall be inserted. Then, connect the input and output of the IBUF to that wire by means of new wires. Select the wire segment (right-click to leave the ``Draw Wires'' mode and return into the ``Select and Drag'' mode) that bypasses the IBUF and remove it (click the scissors button). Finally, drag the IBUF and its connecting wires around until they are in their intended position and shape.
Don't forget to save the changes to the UCF file
do the job).
Click the Implement
item in the Design
pulldown-menu of the Design Manager, and the Implement window appears on
the screen, shown in Figure 16.
Click on the Select
button of the Implement window to select the FPGA type for which the design
shall be implemented. The Part Selector window appears, shown in
In the Part Selector window select the FPGA family
``XC4000XL'' and the device ``XC4010XL'', and click the OK
button. To tell the design manager where to find the UCF file, click
on the Options
button in the Implement window. The Options window, shown in Figure
In the Control Files section add the path to your file adder.ucf in the User Constraints dialog box. Click OK to leave the Options window.
Now, everything is set up to run the hardware
implementation by clicking the Run
button of the Implement window. The Flow Engine window, shown in
Figure 19, appears.
The Flow Engine window shows the progress of the
implementation. In the screendump in Figure
19, the Configure step is running whereas the translation,
mapping, and place&route steps are completed already. Once
the implementation procedure terminates successfully, a bitstream has
been created and has been written into a file named
``adder.bit''. This bitstream contains the configuration
information for the XC4010XL FPGA. We are now ready to check the
completed half-adder design on the XS40 board.
Figure 20 shows a sample
session in a Cygnus shell. First,
the FPGA is configured by running xsload.
Then, all possible combinations of truth values are applied to the input
pads, using xsport.
Fix: Click on the text, for example ADDER1.SCH, rather than the associated icon to open the schematics editor.
Fix: There are two ways to return to the Select-and-Drag mode: (1) Click on the arrow button of the vertical tool bar of the Schematic Editor window; it's the buttom at the top.  (2) Hit the Esc button.
Fix: Move the cursor into the portion of Waveform Viewer window where the waveforms are displayed. Right-click the mouse, choose the Delete menu and left-click on All Waveforms with Power On.
You can also restart the simulation from scratch by pushing the red ON button, or selecting Power On/Reset in the Device pull-down menu of the Waveform Viewer. Although the waveforms remain displayed, the simulator is actually reset. Note that the red simulation-time curser (vertical line) in the waveform graph jumps back to time 0. Running a new simulation step overwrites the current waveform graph.
Fix: Add input (ibuf) and output buffers (obuf) to all input and output wires of the design.
Quirk: I receive error messages when using input pins 32 or 34 on the XS40 board.
Fix: Pins 32 and 34 are special-purpose pins used to set the configuration mode when the FPGA is powered up. Rather than using conventional input pads, special symbols must be used for these pins. These special symbols are available in the Symbol Toolbox of the Schematic Editor under the names MD0 and MD2. MD0 corresponds to pin 32 and MD2 to pin 34. These mappings must not appear in the UCF file.
Fix: There is an array-like notation you can use in the UCF file. For example, to assign wire 3 of bus B to pin 45, use the following line in the UCF file:
Fix: Depending on the combination of segments, the emitted light may be so weak that it seems recognizable during a lunar eclipse only. Use the seven-segment LED's on the XStend board instead.
Hint: Use the generalized De Morgan's theorem:
F'(X1, X2, ..., Xn) =
FD(X1', X2', ..., Xn').
Set the stimulator frequency of bit B0 of the binary counter to 1GHz. Reset the simulator by pushing the red ON button, and perform the simulation for a long step size of 20ns. Use a resolution of 500ps/div to view the resulting waveform. What can you say about the resulting waveforms.
Repeat the timing simulations for 100MHz, 10MHz and 1MHz. Which conclusions
can you draw from the timing simulations.
This book comes with the Xilinx Student Edition, and provides plenty of useful hints about working efficiently with the Foundation Software.