Foundation Tutorial Hierarchical Design EE348/CS338


 

Hardware  Constraints

Volker Strumpen
Depts. of Electrical Engineering and Computer Science
Yale University
 

    Our prototyping hardware consists of an XS40 board piggybagged on an XStend breadboard. Both boards are from XESS Corporation. The XS40 board hosts the Xilinx XC4010XL FPGA.

    This page lists pin assignment for the following parts:

  1. Seven-Segment LED on XS40 Board
  2. LEDs on XStend Board
  3. Parallel Port Connectivity
  4. DIP Switches on XStend Board
  5. Pushbuttons on XStend Board
  6. External Clock on XS40Board
  7. Memory on XS40 Board
         Hints
         References
 
      We use the following naming convention for the LED segments S0-S6: Seven-Segment LED

    The seven-segment LED on the XS40 board is active-high.
 

LED Segment XC4010XL Pin
S0 25
S1 26
S2 24
S3 20
S4 23
S5 18
S6 19
Radix point not connected
 
 
      There are two seven-segment LEDs on the XStend board. Both are active-low.

The seven-segment LED on the left has the following connections to the FPGA pins:
 

LED Segment XC4010XL Pin
S0 3
S1 4
S2 5
S3 78
S4 79
S5 82
S6 83
Radix point 84
The seven-segment LED on the right has the following connections to the FPGA pins:
 
LED Segment XC4010XL Pin
S0 59
S1 57
S2 51
S3 56
S4 50
S5 58
S6 60
Radix point 28
 

There is row of eight individual LEDs on the XStend board, labelled D1-D8. All LEDs are active-low, and are connected to the FPGA as follows:
 
 

LED XC4010XL Pin
D1 41
D2 40
D3 39
D4 38
D5 35
D6 81
D7 80
D8 10
 
      The XS40 board communicates with your PC via the parallel port. The programs xsload and xsport hide most of the details. It is necessary, however, to know the mapping between the arguments of the xsport program and the FPGA pins to send bitstrings to the FPGA. With the following syntax of the xsport command line
 
xsport B7B6B5B4B3B2B1B0

and no blanks between the bits B0-B7, the assignment to the FPGA pins is as follows, including the pin assignments of the parallel connector (J1):
 
 

xsport Bit XC4010XL Pin DB25 (J1) Pin
B0 44 2
B1 45 3
B2 46 4
B3 47 5
B4 48 6
B5 49 7
B6 32 8
B7 34 9
 

Note that special-purpose pins must be used to access pins 32 and 34!
 
 

    The XStend board has a bank of eight DIP switches. A closed DIP switch pulls the associated pin of the FPGA to ground. The DIP switch connections are as follows:
 
 
DIP Switch XC4010XL Pin
1 7
2 8
3 9
4 6
5 77
6 70
7 66
8 69
 
 
 
      The XStend board has three (green) pushbuttons, two of which are programmable general-purpose pushbottons. They are labelled SPARE and RESET. Both pushbuttons pull the associated pin of the FPGA to ground when pushed, i.e. they are active-low.
 
 
Pushbutton XC4010XL Pin
SPARE 67
RESET 37
 
 
 
      The XS40 board hosts a clock running at 12MHz. It is connected to the FPGA via pin 13.
 
 
  XC4010XL Pin
Clock 13
 
 
      The XS40 board hosts a 32 KByte static RAM chip. It has 15 address pins A0-A14, 8 data pins D0-D7, and three active-low control pins:
write enable \WE, output enable \OE, and chip select \CS. The corresponding connections with FPGA pins are as follows:
 
 
Memory Pin XC4010XL Pin
A0 3
A1 4
A2 5
A3 78
A4 79
A5 82
A6 83
A7 84
A8 59
A9 57
A10 51
A11 56
A12 50
A13 58
A14 60
D0 41
D1 40
D2 39
D3 38
D4 35
D5 81
D6 80
D7 10
\CS 65
\OE 61
\WE 62
 
 
 
 
      Use the XC4010XL-pin numbers in the User Constraint File (UCF) when compiling a design for the FPGA. Here is an example for connecting the external clock connected to pin 13 to an input pad named CLK:
 
NET CLK        LOC=P13;
 
Don't forget the semicolon!
 
 
 

    References

  1. Dave Van den Bout, The Practical Xilinx Designer Lab Book, Prentice Hall, Upper Saddle River, 1998.
  2. This book comes with the Xilinx Student Edition, and provides plenty of useful hints about working efficiently with the Foundation Software.


Last  updated: $Date: 1998/10/27 14:01:52 $ by $Author: strumpen $
Copyright © 1998 Volker Strumpen
$Id: hardware.html,v 1.7 1998/10/27 14:01:52 strumpen Exp $