Foundation Tutorial Hardware Constraints EE348/CS338


Hierarchical  Design

Volker Strumpen
Depts. of Electrical Engineering and Computer Science
Yale University

    This part of the tutorial for the Xilinx Foundation Software treats aspects of hierarchical design.  The key aspects are (1) transforming an existing schematic into a module, (2) building a module, potentially consisting of submodules, from scratch, and (3) interconnecting modules via buses.  We expand the half-adder circuit into a full-adder module, and build a 4-bit ripple-carry adder module, as shown in Figure 8, in a hierarchical fashion.  Note that in Foundation terminology a module is also called a macro.

    This tutorial is for the Foundation Series Software, Version 1.4, running on the lab machines.  In particular, screen dumps have been generated from that version.  Several details in the Xilinx Student Edition deviate slightly from this description.  I explain the differences in the text.

    The tutorial on hierarchical design contains the following steps:

  1. Creating a Module from an Existing Schematic
  2. Creating a Module from Scratch
  3. Preparing a Module for Simulation
  4. Hints for Simulation
        Hints and Quirks


    This section explains how to create a full-adder circuit and encapsulate it in a module. Rather than starting from scratch, we reuse the half-adder schematic developed in the tutorial.  One way of reusing an existing schematic is the following:
  1. From the Project Manager, load the half-adder schematic ``adder1.sch'' into the Schematic Editor.  In the File menu of the Schematic Editor, click on Save As ... and save the schematic as a new Sheet with name ``adder2''.
  2. When returning the Project Manager window, the original schematic file ``adder1.sch'' has disappeared.  We can salvage the file and get it back into the project hierarchy by selecting the Add option in the Document pull-down menu of the Project Manager, and clicking on  file ``adder1''.  Similarily, we can remove a file from the project hierarchy again by clicking on the Remove option of the Document pull-down menu.  You may or may not include schematic ``adder1'' in the adder project.  You are likely to run into trouble with that later anyway; see Hints and Quirks.
    We create the full-adder in sheet ``adder2''.  The Schematic Editor contains the half-adder circuit.  Remove the input and output buffers from the half-adder schematic.  Deleting a symbol requires selecting the symbol by means of a left-click, and clicking the delete button (sissors symbol) in the toolbar.  Note, however, that deleting a symbol connected to a terminal such as the IBUFs and OBUFs, for example, will delete the terminal as well!  To delete the selected symbol only, you need to disconnect the symbol from its connecting wires before deleting it.  Click the Disconnect symbol botton in the toolbar (sixth from the right) to that end.  Continue editing by changing the half-adder into the full-adder desgin as shown in Figure 1 below.


Full adder circuit
Figure 1:  Full-adder schematic in Schematic Editor

    To create a module from the full-adder schematic, select the Create Macro Symbol From Current Sheet option in the Hierarchy pull-down menu of the Schematic Editor window.  The Create Symbol window appears, shown in Figure 2.  In the dialog box Symbol Name type ``FULLADD'' and click OK.


Create Symbol window
Figure 2:  Create Symbol window

    Back in the Schematic Editor, you can verify that the full-adder module has been created by opening the Symbol Toolbox, and searching for symbol ``FULLADD.''  Figure 3 shows the new module entry highlighted in the Symbol Toolbox window.


Symbol Toolbox with FULLADD module
 Figure 3:  Symbol Toolbox with FULLADD module

    In the Project Manager, note that sheet ``ADDER2'' disappeared, and sheet ``FULLADD'' has been added to the project library.

    The next step towards a 4-bit adder module is to combine four of the full-adder modules into a 4-bit ripple-carry adder circuit.  We create a new module by selecting option New Symbol Wizard in the Hierarchy pull-down menu of the Schematic Editor.  In the new Design Wizard window, click Next.  The Design Wizard Contents window appears.  Enter ``MYADD4'' in the Symbol Name field, and click Next.

    The Design Wizard Ports window appears, shown in Figure 4.  Here, the inputs and outputs of the new 4-bit adder module are specified.  The module shall have two 4-bit wide input ports for the summands ``A'' and ``B'', and a 1-bit input port ``CIN'' for the incomming carry signal.  Furthermore, a 4-bit wide output port ``SUM'' shall carry the sum signals, and a 1-bit output port ``COUT'' is for the carry-out signal.  Each of the ports is specified by clicking on New, typing the name of the port in the Name field, selecting the Direction of the port, and choosing the bus width of the port with the arrow buttons in the Bus section.  Instead of choosing the bus width by means of the arrow buttons, you can also specify the port as a bus in the Name field using an array notation, for example ``A[3:0].''  Figure 4 shows the Design Wizards Ports window after all input and output ports have been specified.


Design Wizard Ports window
 Figure 4:  Design Wizard with port specifications for the 4-bit adder module ``MYADD4''.

    Click Next to enter the Design Wizard Attributes window, where comments can be added to the module.  Click Next again and subsequently Finish to leave the Design Wizard.  Module ``MYADD4'' has been added to the Symbol Toolbox.  Now that we have the nutshell for the new module, we can create the schematic for its internals.

    If the Symbol Wizard does not generate a new sheet with the terminals of the new module ``MYADD4,'' as shown in Figure 5, the following steps will open a new sheet.  In the File pull-down menu of the Schematic Editor, select New Sheet and create a new, empty sheet entitled ``ADDER3.''  Open the Symbol Toolbox and insert module MYADD4.  Select the Hierarchy Push option in the Hierarchy pull-down menu of the Schematic Editor.  An upper-case ``H'' appears attached to the cursor.  Double-left-click module MYADD4, and a new sheet will appear with the internals of this module.  Leave the Hierarchy Push/Pop mode by right-clicking the mouse.  Figure 5 shows the Schematic Editor window with the new sheet for module MYADD4:


Empty module MYADD4
 Figure 5:  Schematic Editor sheet of empty MYADD4.

    Note that the new sheet contains terminals for all input and output ports of module MYADD4 already.  The terminals for the 4-bit wide ports A, B, and SUM are so-called bus terminals.  Buses are the analogous abstraction for interconnections that modules are for the logic.  Logic is grouped into modules to hide the details of the implementation of a module.  Wires are grouped into buses to hide the details of interconnections between modules.

    The following steps explain how to assemble the 4-bit ripple-carry adder module.  First, drag four FULLADD modules into the editor, and generate the wire connections as shown in Figure 6.


MYADD4 with full-adder modules
 Figure 6:  Schematic Editor sheet of MYADD4 with full-adder modules and 1-bit wiring.

   Next, we connect the bus terminals with the corresponding half-adder ports.  First, we extend the buses to run close by the half-adder ports.  Click on the Draw buses button in the vertical tool bar, just beneath the Draw wires button.  Now, left-click on the open bus end of one of the terminals, left-click to cause the bus to go through that position, and double-left-click to end the bus in the desired position.  After double-clicking, a dialog window entitled ``Add Bus Terminal/Label'' appears.  Since we don't need additional terminals click Bus End in that window.  Extend the three buses A, B, and SUM according to Figure 7.


MYADD4 with bus extensions
Figure 7:  Module MYADD4 with bus extensions.

    The last step is to connect individual wires of the bus with the input and output ports of the full-adder, which are 1-bit ports.  In order to connect to a particular wire of a bus, a so-called bus tap is needed.  Enter the Draw bus taps mode by clicking the Draw bus taps button just beneath the Draw buses button in the vertical tool bar.  Click (somewhere) on the bus you want to tap, for example bus B, and choose a particular wire by means of the up and down arrow buttons of your keyboard.  Note that the selected wire is displayed in the status bar at the bottom of the Schematic Editor window, such as ``Expand Bus Tap: B0.''  Assuming that we want to connect bus wire B0 to port B of the topmost full-adder, just left-click on the wire hanging off port B of the that full-adder module.  Note that the selected bus wire in the status bar has been incremented to B1.  To connect B1 to port B of the next lower full-adder, left-click on the wire hanging off port B.  Continue, until the B-ports of the four full-adders are connected to bus B.  Next, left-click bus A and repeat the process to connect the A ports of the full-adders to bus A, and again for bus SUM.  The resulting schematic is shown in Figure 8.  Save the module.


Complete module MYADD4
Figure 8:  Module MYADD4 with bus taps.

   If you entered the MYADD4 sheet via sheet ADDER3, select Hierarchy Pop in the Hierarchy pull-down menu of the Schematic Editor to return to ADDER3.  If you don't have an ADDER3 sheet yet, select New Sheet in the File menu of the Schematic Editor, and create the sheet as described above.  Sheet ADDER3 should now contain module MYADD4.  Figure 9 shows the current state of affairs.


New sheet with module MYADD4
Figure 9:  Module MYADD4 in a new sheet.

    We are now ready to prepare the new module for simulation.

    In order to simulate the timing behavior of the adder module its ports must be connected to input and output pads (terminals).  If we were going to implement the module, additional input and output buffers (ibufs and obufs) are required as well.

    There are two ways to add bus terminals. Choose one of the methods described below to add the busterminals shown in Figure 12.

  1. One way is to left-click on one of the open bus ends of the bus ports of module MYADD4 and double-left-click at the desired position where the bus terminal shall be placed.  The bus terminal window shown in Figure 10 appears.  We have seen this window already when extending the buses shown in Figure 7.  Enter the name of the bus terminal in the Bus Name field.  Select the terminal type in the I/O Marker selector.  Finally, choose the bus width with the arrow buttons to the right of the Bus Name field.  Click OK to leave add the terminal to the schematic.  The method just described is (probably) the fastest method of adding bus terminals in a situation as shown in Figure 9.


    Bus terminal window
    Figure 10:  Bus terminal window.
  2. In other situations, you may want to add a terminal to an existing bus end.  Optionally, extend the bus ports of module MYADD4 as shown in Figure 11.  To do so, enter the Draw buses mode, left-click first at the new open end of the bus, and only then left-click on the open bus end of the bus port of module MYADD4.  Now, back in Select and Drag mode, double-left-click on the open bus end, and the bus terminal window shown in Figure 10 appears.  Follow the procedure given above to specify the bus terminal.


    Project Manager with new adder hierarchy
    Figure 11:  Module MYADD4 with extended buses.

    Finally, add I/O pads to the ports CIN and COUT.  The resulting schematic is shown in Figure 12.


Project Manager with new adder hierarchy
Figure 12:  Module MYADD4 with bus taps.

    Module MYADD4 is now ready for simulation. Follow the steps described in Section 3 of the tutorial to simulate the behavior of the 4-bit adder.

    To simulate the behavior of the 4-bit adder, follow the steps described in Section 3 of the tutorial.  There are several details you should know when simulating circuits with buses, however.  These details are described in the following.
  1. Adding signals is the same for buses as for wires.  Adding stimulators to a bus is different, however.  Select signals A, B, CIN, SUM, and COUT.  Before adding stimulators, in the waveform viewer, select one of the buses, for example bus A.  Then, pull down the Signal menu, select Bus, and subsequently Flatten.  As a consequence, bus A is flattened and each individual wire is listed.  You can now assign stimulators to each of the wires.
  2. During the simulation, rather than displaying the signals on each individual wire of a bus, you may view the hexadecimal encoding of the signals on the bus.  After having added stimulators to each of the bus wires, in the waveform viewer, select all wires belonging to one bus by left-clicking one of them, holding the SHIFT key or the CTRL key, and left-click on the other wires of the bus.  All wires clicked will be highlighted.  Now, pull down the Signal menu, select Bus, and subsequently Combine.  The bus wires will be combined and only a single entry for the entire bus appears in the waveform viewer.  When running the simulation, the hexadecimal encoding of the bus signals will appear in the waveforms.


    Quirk:  You may run into trouble when starting the simulator due to a Netlist creation error.  The reason for that error is that you might have more than one of the following sheets in the adder project: the original sheet ``adder1'', the new sheet ``adder2,'' the module sheet ``FULLADD'', and the module sheet ``MYADD4.''  If one of the module sheets appears in the Project Manager hierarchy, this indicates that you have edited the internals of the module, but didn't update its netlist.  Each of sheets specifies the input ports A, B, and the output port SUM.  This leads to name clashes during netlist creation! 

    Fix:  If you have edited any of the sheets ``FULLADD,'' or ``MYADD4'' after having created the corresponding modules, you need to update those modules.  In the Schematic Editor, enter each of the sheets, select the Create Macro Symbol From Current Sheet option in the Hierarchy pull-down menu, and overwrite the original macro. In the Project Manager, use the Document pull-down menu to Add only the ``ADDER3'' sheet to the project, and Remove all other sheets as described in Section 1.

Last  updated: $Date: 1998/10/06 14:13:58 $ by $Author $
Copyright © 1998 Volker Strumpen
$Id: hierarchy.html,v 1.4 1998/10/06 14:13:58 strumpen Exp $