|Foundation Tutorial||Hardware Constraints||EE348/CS338|
This part of the tutorial for the Xilinx Foundation Software treats aspects of hierarchical design. The key aspects are (1) transforming an existing schematic into a module, (2) building a module, potentially consisting of submodules, from scratch, and (3) interconnecting modules via buses. We expand the half-adder circuit into a full-adder module, and build a 4-bit ripple-carry adder module, as shown in Figure 8, in a hierarchical fashion. Note that in Foundation terminology a module is also called a macro.
This tutorial is for the Foundation Series Software, Version 1.4, running on the lab machines. In particular, screen dumps have been generated from that version. Several details in the Xilinx Student Edition deviate slightly from this description. I explain the differences in the text.
The tutorial on hierarchical design contains the following steps:
To create a module from the full-adder schematic, select the Create Macro Symbol From Current Sheet option in the Hierarchy pull-down menu of the Schematic Editor window. The Create Symbol window appears, shown in Figure 2. In the dialog box Symbol Name type ``FULLADD'' and click OK.
Back in the Schematic Editor, you can verify that the full-adder module has been created by opening the Symbol Toolbox, and searching for symbol ``FULLADD.'' Figure 3 shows the new module entry highlighted in the Symbol Toolbox window.
In the Project Manager, note that sheet ``ADDER2''
disappeared, and sheet ``FULLADD'' has been added to the project library.
The Design Wizard Ports window appears, shown in Figure 4. Here, the inputs and outputs of the new 4-bit adder module are specified. The module shall have two 4-bit wide input ports for the summands ``A'' and ``B'', and a 1-bit input port ``CIN'' for the incomming carry signal. Furthermore, a 4-bit wide output port ``SUM'' shall carry the sum signals, and a 1-bit output port ``COUT'' is for the carry-out signal. Each of the ports is specified by clicking on New, typing the name of the port in the Name field, selecting the Direction of the port, and choosing the bus width of the port with the arrow buttons in the Bus section. Instead of choosing the bus width by means of the arrow buttons, you can also specify the port as a bus in the Name field using an array notation, for example ``A[3:0].'' Figure 4 shows the Design Wizards Ports window after all input and output ports have been specified.
Click Next to enter the Design Wizard Attributes window, where comments can be added to the module. Click Next again and subsequently Finish to leave the Design Wizard. Module ``MYADD4'' has been added to the Symbol Toolbox. Now that we have the nutshell for the new module, we can create the schematic for its internals.
If the Symbol Wizard does not generate a new sheet with the terminals of the new module ``MYADD4,'' as shown in Figure 5, the following steps will open a new sheet. In the File pull-down menu of the Schematic Editor, select New Sheet and create a new, empty sheet entitled ``ADDER3.'' Open the Symbol Toolbox and insert module MYADD4. Select the Hierarchy Push option in the Hierarchy pull-down menu of the Schematic Editor. An upper-case ``H'' appears attached to the cursor. Double-left-click module MYADD4, and a new sheet will appear with the internals of this module. Leave the Hierarchy Push/Pop mode by right-clicking the mouse. Figure 5 shows the Schematic Editor window with the new sheet for module MYADD4:
Note that the new sheet contains terminals for all input and output ports of module MYADD4 already. The terminals for the 4-bit wide ports A, B, and SUM are so-called bus terminals. Buses are the analogous abstraction for interconnections that modules are for the logic. Logic is grouped into modules to hide the details of the implementation of a module. Wires are grouped into buses to hide the details of interconnections between modules.
The following steps explain how to assemble the 4-bit ripple-carry adder module. First, drag four FULLADD modules into the editor, and generate the wire connections as shown in Figure 6.
Next, we connect the bus terminals with the corresponding half-adder ports. First, we extend the buses to run close by the half-adder ports. Click on the Draw buses button in the vertical tool bar, just beneath the Draw wires button. Now, left-click on the open bus end of one of the terminals, left-click to cause the bus to go through that position, and double-left-click to end the bus in the desired position. After double-clicking, a dialog window entitled ``Add Bus Terminal/Label'' appears. Since we don't need additional terminals click Bus End in that window. Extend the three buses A, B, and SUM according to Figure 7.
The last step is to connect individual wires of the bus with the input and output ports of the full-adder, which are 1-bit ports. In order to connect to a particular wire of a bus, a so-called bus tap is needed. Enter the Draw bus taps mode by clicking the Draw bus taps button just beneath the Draw buses button in the vertical tool bar. Click (somewhere) on the bus you want to tap, for example bus B, and choose a particular wire by means of the up and down arrow buttons of your keyboard. Note that the selected wire is displayed in the status bar at the bottom of the Schematic Editor window, such as ``Expand Bus Tap: B0.'' Assuming that we want to connect bus wire B0 to port B of the topmost full-adder, just left-click on the wire hanging off port B of the that full-adder module. Note that the selected bus wire in the status bar has been incremented to B1. To connect B1 to port B of the next lower full-adder, left-click on the wire hanging off port B. Continue, until the B-ports of the four full-adders are connected to bus B. Next, left-click bus A and repeat the process to connect the A ports of the full-adders to bus A, and again for bus SUM. The resulting schematic is shown in Figure 8. Save the module.
If you entered the MYADD4 sheet via sheet ADDER3, select Hierarchy Pop in the Hierarchy pull-down menu of the Schematic Editor to return to ADDER3. If you don't have an ADDER3 sheet yet, select New Sheet in the File menu of the Schematic Editor, and create the sheet as described above. Sheet ADDER3 should now contain module MYADD4. Figure 9 shows the current state of affairs.
We are now ready to prepare the new module for
There are two ways to add bus terminals. Choose one of the methods described below to add the busterminals shown in Figure 12.
Finally, add I/O pads to the ports CIN and COUT. The resulting schematic is shown in Figure 12.
Module MYADD4 is now ready for simulation.
Follow the steps described in
Section 3 of the tutorial to simulate
the behavior of the 4-bit adder.
Quirk: You may run into trouble when starting the simulator due to a Netlist creation error. The reason for that error is that you might have more than one of the following sheets in the adder project: the original sheet ``adder1'', the new sheet ``adder2,'' the module sheet ``FULLADD'', and the module sheet ``MYADD4.'' If one of the module sheets appears in the Project Manager hierarchy, this indicates that you have edited the internals of the module, but didn't update its netlist. Each of sheets specifies the input ports A, B, and the output port SUM. This leads to name clashes during netlist creation!
If you have edited any of the sheets ``FULLADD,'' or
``MYADD4'' after having created the corresponding modules, you need to
update those modules. In the Schematic Editor, enter each of the
sheets, select the Create Macro Symbol From
Current Sheet option in the Hierarchy pull-down menu, and overwrite the
original macro. In the Project Manager, use the Document pull-down menu to Add only the ``ADDER3'' sheet to the
project, and Remove all other
sheets as described in Section 1.