ISE Foundation Tutorial Hardware Constraints ISE for Tcl Aficionados


Hierarchical  Design

Volker Strumpen
Austin Research Laboratory

    This part of the tutorial for the Xilinx Foundation Software treats aspects of hierarchical design.  The key aspects are (1) transforming an existing schematic into a module, (2) building a module, potentially consisting of submodules, from scratch, and (3) interconnecting modules via buses.  We expand the half-adder circuit into a full-adder module, and build a 4-bit ripple-carry adder module, as shown in Figure 8, in a hierarchical fashion.  Note that in Foundation terminology a module is also called a macro.

    This tutorial is for the ISE Foundation Software, Version 8.2i.  Screen dumps have been generated from that version on a Linux system.

    The tutorial on hierarchical design contains the following steps:

  1. Creating a Module from an Existing Schematic
  2. Creating a Module from Scratch
  3. Preparing a Module for Simulation


    This section explains how to create a full-adder circuit and encapsulate it in a module. Rather than starting from scratch, we reuse the half-adder schematic developed in this tutorial.  One way of reusing an existing schematic is the following:
  1. Within the Project Navigator, load the half-adder schematic ``halfadder.sch'' into the Schematic Editor.  In the File menu of the Schematic Editor, click on Save As ... and save the schematic as a new file with name ``fulladder.sch''.
  2. When returning the Project Navigator window, the new schematic file ``fulladder.sch'' is not shown in the Sources tab of the Sources window.  We need to add the new source file explicitly to the project hierarchy by selecting the Add Source option in the Project pull-down menu of the Project Navigator, and selecting file ``fulladder'' in the popup window.  Similarily, we can remove a file from the project hierarchy again by clicking on the Remove option of the Source pull-down menu.
    We now create the full-adder in sheet ``fulladder.sch''.  The Schematic Editor contains the half-adder circuit.  Remove the inverters and or-gates from the half-adder schematic.  Deleting a symbol requires selecting the symbol by means of a left-click, and clicking the delete button (sissors symbol) in the toolbar.  Add the new symbols: one and2, two xor2, and on or3 gate.  Continue editing by changing the half-adder into the full-adder desgin as shown in Figure 1 below.


Full adder circuit
Figure 1:  Full-adder schematic in Schematic Editor

    To create a module from the full-adder schematic, double the Create Schematic Symbol entry in the Design Utilities menu of the Processes window, as highlighted in Figure 1 already.  The console window acknowledges this action with a message Process "Create Schematic Symbol" completed successfully.  Next, pull down the Tools menu and select Symbol Wizard.  A popup window appears with the Symbol Wizard, shown in Figure 2 below.  Select Using Schematic (with name fulladder), hit Next a couple of times, and then Finish.


Wizard window
Figure 2: Symbol Wizard window

    Back in the Schematic Editor (fulladder.sch), you can verify that the full-adder module has been created by opening the Symbol tab, and searching for symbol ``fulladder'' in your project directory.  Figure 3 shows the new module entry highlighted in the Symbol tab window.


Symbol Toolbox with FULLADD module
 Figure 3:  Symbol Tab with fulladder module

    In the workspace of the Project Navigator, you have a new sheet ``fulladder.sym''.  If you don't like the arrangement of the inputs and outputs, you can change those with the help of the Symbol Wizard.

    The next step towards a 4-bit adder module is to combine four of the full-adder modules into a 4-bit ripple-carry adder circuit.  We create a new module by selecting option New Source in the Project pull-down menu of the Project Navigator.  In the New Source Wizard window, select Schematic and enter File name rippleadder.  Click Next and Finish, and an empty Schematic sheet appears in the Workspace window.

    Next, we specify the ports of our new module. Pull down the Tools menu of the Project Navigator and select Create I/O Markers.  The popup window shown in Figure 4 appears.  Here, we specify the inputs and outputs of our new 4-bit adder module.  The module shall have two 4-bit wide input ports for the summands ``A'' and ``B'', and a 1-bit input port ``CIN'' for the incomming carry signal.  Furthermore, a 4-bit wide output port ``SUM'' shall carry the sum signals, and a 1-bit output port ``COUT'' is for the carry-out signal.  Each of the ports is specified entering them directly in the corresponding fields:

  1. In the Inputs field enter: A(3:0), B(3:0), CIN

  2. In the Outputs field enter: SUM(3:0), COUT
Then, click on Ok.

Create I/O
Markers window
 Figure 4:  Create I/O Marker window with port specifications for the 4-bit adder module.

    After the creation of the I/O markers, the Workspace window contains the Schematic Editor with the nutshell for our ripple-carry adder.  The I/O markers are already placed in the sheet, as shown in Figure 5.

Nutshell for
ripple-carry adder
 Figure 5: Schematic Editor with nutshell for 4-bit ripple-carry adder.

    Note that the I/O markers for the 4-bit wide ports A, B, and SUM are drawn fatter than the other markers.  These I/O markers are so-called bus terminals.  Buses are the analogous abstraction for interconnections that modules are for logic.  Logic is grouped into modules to hide the details of the implementation of a module.  Wires are grouped into buses to hide the details of interconnections between modules.

    The following steps explain how to assemble the 4-bit ripple-carry adder module.  First, drag four fulladder modules into the editor sheet, and generate the wire connections as shown in Figure 6.

with four full-adder modules
 Figure 6: Schematic with four full-adder modules and 1-bit wiring.

   Next, we connect the buses with the corresponding full-adder ports, which are 1-bit ports.  In order to connect to a particular wire of a bus, a so-called bus tap is needed.  From the Add pull-down menu select Bus Tap.  In the Options tab, select the direction for the tap, ``left'' for the taps for buses A and B, and ``right'' for the taps for bus SUM.  Then, place the taps as shown in Figure 7.

Ripple-carry adder with bus taps
Figure 7: Ripple-carry adder with bus taps

   As the last step of the schematic input, we connect the bus taps by means of wires with the corresponding full-adder ports.  Enter the Add Wire mode, left-click on the open tap connection, hold the left mouse button, drag the mouse over the corresponding adder port, and release the left mouse button.  Connect all bus taps as shown in Figure 8 below.

   We have yet to specify the particular bus wire that we tap and connect to the half-adder ports.  To that end, we name the wires that connect the taps with the ports.  From the Add pull-down menu select Net Name.  To make our life easier, select Increase the name in the Options tab.&nsbp; Furthermore, in the Name field of the Options tab enter A(0).  Now, left-click on the wire that connects the tap of bus A with input port A of the topmost full-adder.  Note that the index field in the Name field of the Options tab increments to the new name A(1).  Left-click on the wire at port A of the next lower full-adder, and proceed downwards.  Then, change the Name field to B(0) and connect the B input ports from top to bottom, and finally the SUM output ports.  The resulting schematic is shown in Figure 8.  Save the schematic.

ripple-carry adder module
Figure 8: Complete ripple-carry adder schematic

   Finally, we modularize our ripple-carry adder by creating a schematic symbol, as we did before for the full-adder already.  In the Sources tab, select the ripple-carry adder, and then double-click on Create Schematic Symbol in the Processes tab.  From the Tools menu, select the Symbol Wizard.  There, select Using Schematic, and pick the rippleadder.  Select the order of the inputs and outputs of the symbol to your liking, and finish the Symbol Wizard.

    We are now ready to prepare the new ripple-carry adder module for simulation and implementation.

    In order to simulate the timing behavior of the adder module its ports must be connected to input and output pads (terminals).  If we want to implement the module, additional input and output buffers (ibufs and obufs) are required as well.  The ISE Foundation inserts these buffers automatically, unless you turn this ``Property'' off.

    We prepare a new circuit that contains the ripple-carry adder module with inputs and outputs only.  From the Project pull-down menu select New Source.  Select Schematic, and enter the Name adder4, for our 4-bit adder.  Once in the schematic editor, select Create I/O Markers from the Tools pull-down menu.  Enter the same inputs and outputs we entered in Figure 4.  Drag a ``rippleadder'' symbol into the editor sheet, and connect it to the ports as shown in Figure 9.


New sheet
with rippleadder module
Figure 9: Module rippleadder in a new sheet.

    Next, we add stimulators as we did in Section 3 of the ISE Tutorial.  The only qualitative difference is that we have to deal with input buses rather than wires.  To avoid the tedious task of toggling values on individual wires, we use the Pattern Wizard to assign signals to input buses A and B.  Figure 10 demonstrates the specification of the stimulators.  Double click on the signal bar associated with input bus A or B at a desired simulation time.  In the popup window Set Value click on the Pattern Wizard button.  The Pattern Wizard enables you to assign relatively fancy stimulus patterns with ease.

Stimulators for adder4 simulation
Figure 10: Adding stimulators for adder4 simulation

    Running the simulation is no different from the half-adder example in the tutorial.

  1. ISE In-Depth Tutorial 8.2, Xilinx, 2006.

  2. Xilinx Development System Reference Guide, Xilinx, 2005.

  3. Hierarchical Design, Foundation Tutorial (Version 1.4), Volker Strumpen, 1998.

Last  updated: Tue Sep 26 20:04:25 CDT 2006
Copyright © 2006 Volker Strumpen