Hierarchical Design Hardware Constraints ISE for Tcl Aficionados


 

Xilinx  ISE  Foundation  Tutorial

Volker Strumpen
Austin Research Laboratory
IBM
 

    This is a brief tutorial for the Xilinx ISE Foundation Software.  It targets first-time users who want to get started with the ISE Foundation Software to synthesize a digital design.  During the course of the tutorial, all steps of the synthesis process are covered using a half-adder as running example.  We start with the input of the circuit in the schematic editor, simulate the timing behavior of the circuit, compile it for a Virtex-4 FPGA, and test the design on an ML405 prototyping board.

    This tutorial is for the ISE Foundation Software, Version 8.2i.  Screen dumps have been generated from that version on a Linux system.

    The tutorial contains the following steps:

  1. Project Manager: How to Create a New Project
  2. Schematic Editor: How to Create a Schematic
  3. Simulator: How to Simululate a Circuit
  4. Implementation: How to Compile into Hardware
  5. Verification: How to Test the Design on an ML405 Board

    The following sections provide additional information:

        Hints
        References    provides pointers to online manuals


    This tutorial is accompanied by the following sections that are also linked at the top of this page:

  1. Hierarchical Design
  2. Hardware Constraints
  3. ISE for Tcl Aficionados (Advanced: read when you're ready to move on beyond the windows interface)

    Start the ISE Project Navigator, called ise on Linux systems.  Pull down the File menu and click on New Project. A new window entitled ``New Project Wizard'' appears.  The state of affairs is shown in Figure 1 below.
 
 
Project Navigator with New Project window
 
Figure 1:  Project Navigator window with popup window for New Project
 

Select a directory for the Project Location in the New Project Wizard window.  Then, in the Project Name field, type ``adder.''  Note that the project name is added automagically to the directory path.  Finally, select Source Type ``Schematic'', and click Next.  The Project Wizard switches to the ``Device Properties'' window.  Select device family Virtex4 and device XC4VFX20, as shown in Figure 2 below.
 
 

Project Navigator with Device Properties window
 
Figure 2:  Project Navigator window with popup window for Device Properties
 

Click Next a couple of times, and Finish to exit the New Project Wizard.  Now, a new project hierarchy is generated and is displayed in the ``Sources Window'' portion in the top left corner of the Project Navigator window shown in Figure 3.  It contains the directory ``adder'', and the entry ``xc4vf...''.  Note that a project is no more than a collection of files in the directory that you chose in the Project Location of Figure 1.  You can browse through that directory by selecting the Open Project item in the File menu of the Project Navigator.
 
 

Project Navigator with new adder project
 
Figure 3:  Project Navigator window with new adder project. 
 

We are now ready to create a schematic for our half-adder.



    In the ``Processes'' window of the Project Navigator, cf. Figure 3, double click on the entry entitled Create New Source.  (Alternatively, pull down the Project menu and click on New Source.)  Select source type Schematic and enter in File name ``halfadder'', as shown in Figure 4 below. 
 
 

Project Navigator with popup window to Select Source Type
 
Figure 4:  Project Navigator with popup window to Select Source Type. 
 

   Click Next and Finish. The Project Navigator window now shows the ``Design Summary'' of the Schematic Editor, see Figure 5.  To switch to the drawing area of the Schematic Editor click on the halfadder.sch tab at the bottom of the ``Workspace'' window.   Later in the design process, clicking on that file name in the Project Manager will automatically start up the Schematic Editor.
 
 

Project Navigator after launching schematic editor
 
Figure 5:  Project Navigator window after launching the schematic editor. 
 

    Note the action of having launched the Schematic Editor is logged in the Transcript portion at the bottom of the Project Navigator window.

    The design of the half-adder that we are about to generate is shown in the Schematic Editor window in Figure 6.


 
 
Adder schematic in Schematic Editor
 
 
Figure 6:  Schematic Editor window with half-adder schematic
 

    A schematic is generated by inserting gates and input/output pads.  The inputs and outputs of the gates and pads are connected by means of wires.  Standard symbols such as the inverter ``inv'', the and-gate ``and2'', and the or-gate ``or2'' can be found in the ``Symbol Browser''.  The Symbol Browser is opened by pulling down the Add menu and selecting Symbol.  Alternatively, the horizontal toolbar offers a button showing a gate symbol above a resistor.  The ``Symbol Browser'' appears to the left of the Schematic editor. Adjust the size of the ``Categories'' and ``Symbols'' portions of the window. A screen dump of the Project Navigator with the Symbol Browser is shown in Figure 7 below.
 
 

Symbol Toolbox
 
Figure 7:  Symbol Browser (left) and Schematic Editor (right)
 

    The symbol browser organizes symbols by category.  Select category Logic, and scroll through the list of combinational gates in the list of Symbols.  According to the naming convention in the symbol browser, gates are listed by a (sort of) descriptive name, such as ``and'' or ``or''.  Most names end with a number, often describing the number of inputs (fan-in) of the gate.  For example, an AND-gate with two inputs and one output is named ``and2''.  Analogously, the name for an or-gate with two inputs and one output is ``or2''.  Gates with a single input don't have the number of inputs appended to the name, as for example for the inverter, which is simply named ``inv''.  You may insert a gate in the drawing area of the Schematic Editor by left-clicking on the name in the Symbols list, and by moving the cursor into the drawing area.  The symbol for the gate appears attached to the cursor.  Moving the mouse drags the gate across the drawing area.  Left-clicking the mouse in the drawing area causes the gate symbol to be inserted at the current mouse position.  This process can be repeated until all gates are positioned approximately where they are intended to end up.  Figure 8 shows the gates dropped for the half-adder.
 
 

Adder gates inserted
 
Figure 8:  Schematic Editor window with gates for half-adder
 

    You can move the gates around by selecting them with a left-click and dragging them across the drawing area.  Releasing the left mouse button drops the gate at the current mouse position.  It is often convenient to change the size of the drawing area by zooming.  In Figure 8 we have zoomed into the drawing area (via the View menu) to enlarge the symbols.  The grid appears automatically, if you zoom in far enough.  Symbols snap to the grid, which simplifies alignment.
 

    The next step is to wire up the circuit.  To enter the ``Draw Wires'' mode, pull down the Add menu and select the Wire item.  Alternatively, there is also an ``Add wire'' button in the horizontal toolbar above the drawing area.  Then, left-click to define one end of the wire, hold the left mouse button, and release it or left-click again at the other end.  The wire is automatically routed in Manhattan style.  Insert all wire connections as shown in Figure 9.  You can leave the ``Draw Wires'' mode by hitting the ESC-button of your keyboard.
 

Add Wires
 
Figure 9:  Schematic Editor window after adding wires.
 
 

    The last step is to add input/output pads to our collection of gates.  Pull down the Add menu and select I/O Marker.  Then, click on the floating ends of the unconnected wires.  Upon each click, a pad symbol appears.  We are left with determining the direction, input or output, and the name for each of the pads.  Double-click on a pad, and a window Net Attributes pops up.  Assign the names A and B to the input pads and SUM and CARRY to the output pads as shown in Figure 6 above to complete the half-adder schematic. Save the design by selecting Save in the File menu.
 


 

    Configure the simulator by selecting Behaviorial Simulation in the Sources For pull-down menu of the Sources tab of the Project Navigator, cf. Figure 10.
 

Select Behavioral Simulation
 
Figure 10:  Preparing for Behavioral Simulation.
 
 

    Next, we create a testbench using the Waveform Generator.  Pull down the Project menu and select New Source.  Select TestBench Waveform as source, and enter File name ``halfadder_tb'', cf. Figure 4.  Click Next twice, and Finish to enter the ``Initial Timing and Clock Wizard.  Change the default parameters to those shown in Figure 11 below.
 

Initialize Timing
 
Figure 11:  Initial Timing and Clock Wizard.
 
 

    After clicking on Finish, the Project Navigator switches to the Waveform Editor window shown in in Figure 12


 
Waveform Viewer
 
Figure 12:  Waveform Editor window of the Behavioral Simulator.

 Two steps are required to produce a behavioral simulation of our half-adder circuit:

  1. Define input signals to stimulate the circuit.
  2. Run the simulation to produce the timing waveforms for the chosen input signals.
We examine each of the three steps in turn.
 

    Simple input signals, so-called stimulators, can be defined easily by means of the Waveform editor.  We wish to apply the sequence of truth values 00, 01, 10, and 11 to the inputs A and B of the half-adder circuit.  In the Waveform Editor, if you left-click the colored areas associated with the time slices of input signals A and B, you toggle the stimulus.  Generate the waveforms shown in Figure 13.


 
 
Figure 13:  Specifying input signals in the Waveform Editor window
 

    Save the testbench waveforms by selecting Save in the File menu.


 

    Having specified the stimulator signals for the inputs, the simulator is ready to run a behavioral simulation of the half-adder circuit.  You run the simulation by first selecting the halfadder_tb item in the Sources window.  Then, in the Processes tab of the Processes window, open the Xilinx ISE Simulator submenu, and double-click Simulate Behavioral Model.  When the simulation is finished, click on the Simulation tab of the Workspace to view the results in the Waveform Viewer.  Figure 14 below shows the results.


 
 
Figure 14:  Run the simulation, and inspect the results in the Waveform viewer
 

 
      Before the half-adder design can be compiled into hardware, one more detail needs to be taken care of:  we must specify the I/O pin assignments of the FPGA.

    The pin assignment within the FPGA can be specified by means of a ``User Constraint File'' (UCF).  To create a UCF file, configure the synthesis tool by selecting Synthesis/Implementation in the Sources For pull-down menu of the Sources tab of the Project Navigator.  The Processes window will now show an entry User Constraints.  Open the entry, and select Edit Constraints (Text).  A popup window appears, asking to confirm the creation of a UCF file; click on Yes.  The workspace turns into a text editor, where you should input the following constraints:

    This will assign input A to pin K8 of the FPGA, input B to pin M6, output SUM to pin A10 and output CARRY to pin B10.  Take a look at the hardware constraints to find out how these pins are connected with the outside world.  The comments shown in Figure 15 provide this information as well.

 

 
Figure 15:  Adding pin assignments with text editor.

 

    Don't forget to save the changes to the UCF file (Ctrl-S will do the job).  This creates a file halfadder.ucf in your project directory, which you can edit with your favorite editor as well.
 

    Note that, unlike in earlier versions of the Foundation tools, there is no need to specify input (IBUF) and ouput buffers (OBUF) any longer.  The synthesis tool inserts these buffers automagically, unless you turn this ``Property'' off.
 

    We are now ready to implement the half-adder design, i.e. compile the FPGA configuration.  In the Processes window, close entry User Constraints, and double click on entry Generate Programming File.  In response, the synthesis engine starts crunching, passing through three stages Synthesis - XST, Implement Design, and Generate Programming FileFigure 16 shows the Project Navigator while synthesis is in progress.  The process is complete when all three stages are marked with a green button with a hitch symbol.

 

 
Figure 16:  Synthesising the design into a bit stream.

 

    Once the implementation process terminates successfully, a bitstream has been created, and has been written into a file named halfadder.bit in your project directory.  This bitstream contains the configuration information for the Virtex-4 FPGA.  We are now ready to check the completed half-adder design on the ML405 board.

 

    There are various ways of downloading the half-adder design into the Virtex-4 FPGA on the ML405 boards.  We describe how to use a CF-card to configure the FPGA by means of the SystemACE controller. 
    The ML405 board has several programmable chips, that can be and have to be configured properly.  We use the impact tool to produce an ace-file that contains the configuration data for each of these chips.  We will describe how to supply the ace-file via the CF-card to the board in Section 5.2 below.

    We will use the impact tool in batch mode. Use your favorite text editor to prepare (or download) the batch file adder.cmd with the following impact commands:

    Note that whis file assumes that your ISE Foundation software is installed in directory /opt/xilinx, and the project directory path is the same as chosen in Figure 1.  This batch file specifies the JTAG chain of three programmable devices on the ML405 board: (1) the platform flash memory chip xcf32p, (2) the Virtex-4 chip, and (3) a CPLD chip xc95144xl.  Since we do not use the flash memory and the CPLD, we configure these devices with the default configuration files ``xcf32p.bsd'' and ``xc95144xl.bsd,'' which effectively deactivate these chips.  For the Virtex-4 chip at position 2 in the JTAG chain, we specify the bitstream file ``halfadder.bit,'' which we created earlier.

    Now, execute the batch file in a shell using the command:

The results can be found in directory addercf, which we specified with the impact command addercf.  This directory has a subdirectory rev0, that we specified in impact command adddesign.  The ace-file rev0.ace can be found in this subdirectory.  The other file addercf/xilinx.sys is an ASCII file which supplies the location of the ace-file to the SystemACE chip xccace on the ML405 board when loading the design.  We describe this process in more detail below.


    We describe how to configure the programmable devices of the ML405 board with a brand new compact flash (CF-card).  We assume you have a host computer and a compact flash reader/writer.  The preparation of the CF-card involves three steps:

  1. Partition the CF-card (optional).
  2. Format a DOS file system.
  3. Copy the configuration data including the ace-file onto the CF-card.
We examine each of the three steps in turn.

   If you have a USB-based card reader, for example, plug the card reader into your host computer's USB port, and use fdisk or sfdisk to examine the partition table.  For example, I partitioned one of my CF-cards as follows:

    The important partition is the bootable FAT16 partition, that the SystemACE chip wants to read when the ML405 board is powered up or reset.  After creating the FAT16 partition, /dev/sda1 in the example above, we create a DOS file system by formatting the partition with the command:

There is some amount of black magic at work here:  the SystemACE chip expects more than one sector per cluster.  Option -s 4 specifies four disk sectors per cluster, which keeps everybody happy.

    Next, we copy our ace-file onto the CF-card. First, we mount the FAT16 partition onto directory /mnt/flash, say:

Then, copy the entire directory addercf that the impact tool generated onto the CF-card.  Assuming that you are in the project directory, execute: Finally, move file ``xilinx.sys'' to the toplevel: By now, the CF-card stores two files: Note that the contents of file ``xilinx.sys'' is little more than a description of where to find the ace-file.


Don't forget to umount /mnt/flash before removing the CF-card.

    Set the switches on the ML405 board as follows:

  1. Set the Configuration Source Selector switch with the three positions CPLD Flash, Platform Flash, and SystemACE to SystemACE.
  2. Set the 6-position DIP Switch to 000111.  The rightmost three ones set the FPGA configuration mode to ``slave serial,'' and the leftmost three zeros selects configuration address zero.

   The configuration address selected by the leftmost three bits of the 6-position DIP switch must be assigned the directory chosen in the impact batch file, rev0 in our case.  The SystemACE controller is capable of selecting one of eight different ace-files.  The configuration addresses of the ace-file are specified in file xilinx.sys generated by the impact tool.  For example, the CF-card that Xilinx ships with the ML405 board uses all eight configuration addresses, as you can see by inspecting file xilinx.sys.;  The version option of the adddesign command in the impact batch file determines the configuration address generated by impact in file xilinx.sys.  For example, impact command

generates the entry in file xilinx.sys.  Analogously, the command generates the entry in file xilinx.sys.  All you need is the corresponding directory for the ace-file, and adjust the dip switches to select the configuration ``version'' to configure the FPGA with that ace-file.  If your CF-card does not have an ace-file maching the dip switch selection, the configuration process will fail, and the red LED DS1 signals an error.


    We are now ready to test our half-adder design: mount the CF-card in the ML405 board and power it up.  The Virtex-4 FPGA will be configured with our half-adder design.  The four GPIO LED's next to the five push buttons should remain off.

    Verify that the lightning of GPIO LED's 0 and 1 corresponds to the output signals SUM and CARRY of the half-adder, when pushing buttons GPIO_SW_W (West) and GPIO_SW_E (East), which are connected to input signals A and B, respectively.



  1. Problem: I closed the Sources and/or Processes portions of the Project Navigator window.  How can I get them back?

    Solution: Pull down the View menu of the Project Navigator, and select Sources and/or Processes.

  2. Problem: How can I switch off the magic IBUF/OBUF generation during synthesis?

    Solution: In the Processes window, right-click on Synthesize - XST, and the Process Properties window pops up.  Select ``Category'' Xilinx Specific Options, and deselect the first entry Add I/O Buffers.

  3. Problem: My project synthesizes for the wrong FPGA device.  How can I choose the proper device?

    Solution: In the Sources tab of the Project Navigator right-click the entry with the chip symbol (see the highlighted entry xc4vf... in Figure 3), and select Properties.  The popup window Project Properties appears, which allows you to choose the device properties like in the New Project Wizard shown in Figure 2.


    Additional documents beyond those listed below can be found in the doc directory of the ISE 8.2i distribution DVD.

  1. ML405 Evaluation Platform--User Guide (UG-210), Xilinx, 2006.

  2. ISE In-Depth Tutorial 8.2, Xilinx, 2006.

  3. iMPACT User Guide, Xilinx, 2002.

  4. Xilinx Development System Reference Guide, Xilinx, 2006.

  5. XST User Guide 8.2i, Xilinx, 2006.

  6. Synthesis and Simulation Design Guide 8.2i, Xilinx, 2006.

  7. Foundation Tutorial (Version 1.4), Volker Strumpen, 1998.

Last  updated: Tue Sep 26 10:44:20 CDT 2006
Copyright 2006 Volker Strumpen