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Xilinx ISE Foundation Tutorial
This is a brief tutorial for the Xilinx ISE
Foundation Software. It targets first-time users who want to get
started with the ISE Foundation Software to synthesize a digital
design. During the course of the tutorial, all steps of the
synthesis process are covered using a half-adder as running
example. We start with the input of the circuit in the schematic
editor, simulate the timing behavior of the circuit, compile it for a
Virtex-4 FPGA, and test the design on an ML405 prototyping
This tutorial is for the ISE Foundation
Software, Version 8.2i. Screen dumps have been generated from
that version on a Linux system.
The tutorial contains the following steps:
The following sections provide additional information:
References provides pointers to online manuals
This tutorial is accompanied by the following sections that are also linked at the top of this page:
Select a directory for the Project
Location in the New Project Wizard window. Then, in
the Project Name field, type
``adder.'' Note that the project name is added automagically to
the directory path. Finally, select Source Type ``Schematic'', and click
Next. The Project Wizard
switches to the ``Device Properties'' window. Select device
Virtex4 and device
XC4VFX20, as shown in
Figure 2 below.
Click Next a couple of times, and
Finish to exit the New Project
Now, a new project hierarchy is generated and is displayed in the
``Sources Window'' portion in the top left corner of the Project
Navigator window shown in Figure 3. It
contains the directory ``adder'', and the entry ``xc4vf...''.
Note that a project is no more than a collection of files in the
directory that you chose in the
Project Location of Figure 1. You can browse through that
directory by selecting the
Open Project item in the File menu of the Project Navigator.
We are now ready to create a schematic for our half-adder.
and Finish. The Project Navigator
window now shows the ``Design Summary'' of the Schematic Editor, see
Figure 5. To switch to the drawing area
of the Schematic Editor click on the halfadder.sch tab at the bottom of the
``Workspace'' window. Later in the design process, clicking on
that file name in the Project Manager will automatically start up the
Note the action of having launched the Schematic Editor is logged in the Transcript portion at the bottom of the Project Navigator window.
The design of the half-adder that we are about to generate is shown in the Schematic Editor window in Figure 6.
A schematic is generated by inserting gates and input/output
pads. The inputs and outputs of the gates and pads are connected by means
of wires. Standard symbols such as the inverter ``inv'', the and-gate
``and2'', and the or-gate ``or2'' can be found in the ``Symbol Browser''.
The Symbol Browser is opened by pulling down the Add menu and selecting Symbol. Alternatively, the
horizontal toolbar offers a button showing a gate symbol above a resistor.
The ``Symbol Browser'' appears to the left of the Schematic editor.
Adjust the size of the ``Categories'' and ``Symbols'' portions of the window.
A screen dump of the Project Navigator with the Symbol Browser
is shown in Figure 7 below.
The symbol browser organizes symbols by
category. Select category Logic, and scroll through the list of
combinational gates in the list of Symbols. According to the
naming convention in the symbol browser, gates are listed by a (sort
of) descriptive name, such as ``and'' or ``or''. Most names end
with a number, often describing the number of inputs (fan-in) of the
gate. For example, an AND-gate with two inputs and one output is
named ``and2''. Analogously, the name for an or-gate with two
inputs and one output is ``or2''. Gates with a single input
don't have the number of inputs appended to the name, as for example
for the inverter, which is simply named ``inv''. You may insert
a gate in the drawing area of the Schematic Editor by left-clicking on
the name in the Symbols list, and by moving the cursor into the
drawing area. The symbol for the gate appears attached to the
cursor. Moving the mouse drags the gate across the drawing
area. Left-clicking the mouse in the drawing area causes the
gate symbol to be inserted at the current mouse position. This
process can be repeated until all gates are positioned approximately
where they are intended to end up. Figure
8 shows the gates dropped for the half-adder.
You can move the gates around by selecting them
with a left-click and dragging them across the drawing area.
Releasing the left mouse button drops the gate at the current mouse
position. It is often convenient to change the size of the
drawing area by zooming. In Figure 8 we
have zoomed into the drawing area (via the View menu) to enlarge the symbols.
The grid appears automatically, if you zoom in far enough.
Symbols snap to the grid, which simplifies alignment.
The next step is to wire up the circuit.
To enter the ``Draw Wires'' mode, pull down the Add menu and select the Wire item. Alternatively, there is
also an ``Add wire'' button in the horizontal toolbar above the
drawing area. Then, left-click to define one end of the wire,
hold the left mouse button, and release it or left-click again at the
other end. The wire is automatically routed in Manhattan
style. Insert all wire connections as shown in
Figure 9. You can leave the ``Draw Wires'' mode by
hitting the ESC-button of your keyboard.
The last step is to add input/output pads to our
collection of gates. Pull down the Add menu and select I/O Marker. Then, click on the
floating ends of the unconnected wires. Upon each click, a pad
symbol appears. We are left with determining the direction,
input or output, and the name for each of the pads. Double-click
on a pad, and a window
Net Attributes pops up.
Assign the names A and B to the input pads and
SUM and CARRY to the output pads as shown in Figure 6 above to complete the half-adder
schematic. Save the design by selecting Save in the File menu.
Configure the simulator by selecting Behaviorial Simulation in the Sources For pull-down menu of the Sources
tab of the Project Navigator, cf. Figure 10.
Next, we create a testbench using the Waveform
Generator. Pull down the Project menu and select New Source. Select TestBench Waveform as source, and enter
File name ``halfadder_tb'', cf. Figure 4. Click Next twice, and Finish to enter the ``Initial Timing and
Clock Wizard. Change the default parameters to those shown in Figure 11 below.
After clicking on Finish, the Project Navigator switches to the Waveform Editor window shown in in Figure 12
Two steps are required to produce a behavioral simulation of our half-adder circuit:
Simple input signals, so-called stimulators, can be defined easily by means of the Waveform editor. We wish to apply the sequence of truth values 00, 01, 10, and 11 to the inputs A and B of the half-adder circuit. In the Waveform Editor, if you left-click the colored areas associated with the time slices of input signals A and B, you toggle the stimulus. Generate the waveforms shown in Figure 13.
Save the testbench waveforms by selecting Save in the File menu.
Having specified the stimulator signals for the inputs, the simulator is ready to run a behavioral simulation of the half-adder circuit. You run the simulation by first selecting the halfadder_tb item in the Sources window. Then, in the Processes tab of the Processes window, open the Xilinx ISE Simulator submenu, and double-click Simulate Behavioral Model. When the simulation is finished, click on the Simulation tab of the Workspace to view the results in the Waveform Viewer. Figure 14 below shows the results.
The pin assignment within the FPGA can be specified by means of a ``User Constraint File'' (UCF). To create a UCF file, configure the synthesis tool by selecting Synthesis/Implementation in the Sources For pull-down menu of the Sources tab of the Project Navigator. The Processes window will now show an entry User Constraints. Open the entry, and select Edit Constraints (Text). A popup window appears, asking to confirm the creation of a UCF file; click on Yes. The workspace turns into a text editor, where you should input the following constraints:
Don't forget to save the changes to the UCF file
do the job). This creates a file halfadder.ucf in your project directory,
which you can edit with your favorite editor as well.
Note that, unlike in earlier versions of the
Foundation tools, there is no need to specify input (IBUF) and ouput
buffers (OBUF) any longer. The synthesis tool inserts these
buffers automagically, unless you turn this ``Property'' off.
Once the implementation process terminates successfully, a bitstream has been created, and has been written into a file named halfadder.bit in your project directory. This bitstream contains the configuration information for the Virtex-4 FPGA. We are now ready to check the completed half-adder design on the ML405 board.
We will use the impact tool in batch mode. Use your favorite text editor to prepare (or download) the batch file adder.cmd with the following impact commands:
Note that whis file assumes that your ISE Foundation software is installed in directory /opt/xilinx, and the project directory path is the same as chosen in Figure 1. This batch file specifies the JTAG chain of three programmable devices on the ML405 board: (1) the platform flash memory chip xcf32p, (2) the Virtex-4 chip, and (3) a CPLD chip xc95144xl. Since we do not use the flash memory and the CPLD, we configure these devices with the default configuration files ``xcf32p.bsd'' and ``xc95144xl.bsd,'' which effectively deactivate these chips. For the Virtex-4 chip at position 2 in the JTAG chain, we specify the bitstream file ``halfadder.bit,'' which we created earlier.
Now, execute the batch file in a shell using the command:
The results can be found in directory addercf, which we specified with the impact command addercf. This directory has a subdirectory rev0, that we specified in impact command adddesign. The ace-file rev0.ace can be found in this subdirectory. The other file addercf/xilinx.sys is an ASCII file which supplies the location of the ace-file to the SystemACE chip xccace on the ML405 board when loading the design. We describe this process in more detail below.
We describe how to configure the programmable devices of the ML405 board with a brand new compact flash (CF-card). We assume you have a host computer and a compact flash reader/writer. The preparation of the CF-card involves three steps:
If you have a USB-based card reader, for example, plug the card reader into your host computer's USB port, and use fdisk or sfdisk to examine the partition table. For example, I partitioned one of my CF-cards as follows:
The important partition is the bootable FAT16 partition, that the SystemACE chip wants to read when the ML405 board is powered up or reset. After creating the FAT16 partition, /dev/sda1 in the example above, we create a DOS file system by formatting the partition with the command:
Next, we copy our ace-file onto the CF-card. First, we mount the FAT16 partition onto directory /mnt/flash, say:
Set the switches on the ML405 board as follows:
The configuration address selected by the leftmost three bits of the 6-position DIP switch must be assigned the directory chosen in the impact batch file, rev0 in our case. The SystemACE controller is capable of selecting one of eight different ace-files. The configuration addresses of the ace-file are specified in file xilinx.sys generated by the impact tool. For example, the CF-card that Xilinx ships with the ML405 board uses all eight configuration addresses, as you can see by inspecting file xilinx.sys.; The version option of the adddesign command in the impact batch file determines the configuration address generated by impact in file xilinx.sys. For example, impact command
We are now ready to test our half-adder design: mount the CF-card in the ML405 board and power it up. The Virtex-4 FPGA will be configured with our half-adder design. The four GPIO LED's next to the five push buttons should remain off.
Verify that the lightning of GPIO LED's 0 and 1 corresponds to the output signals SUM and CARRY of the half-adder, when pushing buttons GPIO_SW_W (West) and GPIO_SW_E (East), which are connected to input signals A and B, respectively.
Additional documents beyond those listed below can be found in the doc directory of the ISE 8.2i distribution DVD.